The present invention is related in general to hardware description languages (HDLs) and in particular to a method of performing testbench tests in a HDL to avoid task collisions.
Hardware description languages (HDLs) are high level languages used to design, test, and document electronic systems. HDLs allow designers to design at various levels of abstraction. There are several HDLs currently in use. Among them are Verilog and VHDL.
When designing a field programmable gate array (FPGA), an applications specific integrated circuit (ASIC), or other logic device, a simulation environment that includes a xe2x80x9ctestbenchxe2x80x9d and the design under test (DUT) must be created. This environment allows tests to be generated to check the functionality of the logic device that has been created in the HDL. In many instances these tests, which are usually written in the same HDL as the DUT, must communicate with the logic device through a common interface such as a microprocessor interface. The logic device may have many internal blocks of unrelated logic, but must interface through the microprocessor interface, which can present a bottleneck. For example, if two tests are run at the same time, both tests may call tasks that attempt to access the microprocessor interface at the same time, which can cause a test bench task collision. If this occurs, the results can be undeterminable. The present invention provides a method to run concurrent tests on a logic device under test and avoid the problem of task collisions, thus resulting in considerable time savings in the HDL design process.